In an exemplary scenario, the testing of semiconductor designs may be an integral step in the manufacturing process, and may involve a variety of challenges, such as, for example, using exhaustive test patterns and, at the same time, reducing overall test time and the cost involved in the testing of the designs. Some exemplary techniques for reducing the test time and cost involved in testing may include designing the devices under test (DUTs) with adequate design for testability (DFT) techniques that are amenable for Automatic Test Pattern Generation (ATPG) and ATPG tools so as to support a test application using different testers. Examples of some testers may include a very low cost tester (VLCT) or high-end testers.
In various exemplary scenarios, a majority of the hardware implementations in DUTs for the tester, as well as for the correct operation with ATPG tool generated patterns, perform scan-in shift and scan-out shift operations in tandem. In various cases, a desired controllability (based on the scan-in operation) and desired observability (based on scan-out operations) may be different, and, in such cases, some test cycles and associated resources may not be fully utilized. An example of such a case may include the testing of multiple, identical/non-identical cores. For instance, in certain devices, the quantity of data that is to be shifted in is not necessarily the same as the quantity of data that is to be shifted out on a per test pattern basis. Another example (where the desired controllability and the desired observability may be different) of such a case is where portions of the scan channels are to be scanned in or scanned out. Another such case may be where the same scan-in value in a particular module can be used to test for faults in other adjacent modules across more than one test pattern. Another case is where the initialization of several modules may require several scan-in operations in order to set the states of the individual scan chains of different modules, while the observation of a fewer number of scan chains may be sufficient on a per pattern basis in order to obtain the targeted coverage.
Further, as Input/Output (I/O) ports of the DUTs are coupled with corresponding ports of the tester, the frequency of the clock which controls the scan-in or scan-out shift operations is constrained by (1) the speed of the data transfer in the tester scan channels and (2) the matching of the DUT I/Os with the loads seen on the testing system's boards for this clock frequency. In various scenarios, the DUT's output ports may not have sufficient drive strength to drive the load on the connection between the DUT and the VLCT, and the low strength I/Os may impair shift speed and may also impact test time.